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參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 47/150頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
47
6.1
System Interface Considerations
When using the CD1865, two areas where system architects, designers, and programmers should
consider options are system clock speed, and unclocked versus clocked-host bus interface.
6.2
System Clock and Bit Rate Options
6.2.1
System Clock
System clock is a high-frequency clock (supplied by the user) used by the CD1865 to receive all
the necessary timing. The CD1865 is capable of handling system clock levels of TTL-compatible
voltage swings; however, the V
IL
and V
IH
specifications are not identical to all families of TTL
logic. Specifically, the clock signal (and the reset signal) have lower V
IL
and higher V
IH
than the
worst-case specifications of some TTL families. In general, any TTL family is adequate if not
heavily loaded. Refer to the DC Specifications in
Section 10.3
for details.
××××××
The CD1865 can be operated from the main system clock or its own clock. Operation from
the main system clock can reduce the number of clocks required, and it allows the bus interface
between the system and the CD1865 to be clocked, but in general, typical system clock speeds are
not exact baud-rate multiples. As bit rates are received from the clock, it is important to consider
this when selecting a clock value. If exact baud rates are needed, or the system clock is not a
convenient value, the CD1865 must be supplied with its own clock or crystal.
6.2.2
External Clock
It is recommended that the 2
×
-clock option (oscillator or crystal) be used wherever possible.
Figure
15
shows a possible design configuration for the clock circuitry if the crystal is being used. Please
refer to the CD1865 Evaluation Kit documentation for details on the design configurations used.
The crystal used for the evaluation board is a 66-MHz third overtone part.
Figure 15. 2
×
Clock Option
OSC 2
OSC 1
200K
–
500K
33 pF
33 pF
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