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參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 11/150頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
11
Because the CD1865 RISC processor is processing every character sent or received, features such
as automatic flow control and special character recognition are easily implemented. This further
reduces the processing burden on the host system. Both In-Band (Xon, Xoff) and Out-of-Band
(RTS/CTS, DTR) Flow-Control modes are supported. For in-band flow control, the CD1865
automatically starts and stops its transmitter when the remote unit sends flow-control characters.
The CD1865 also makes it easy for the local host to flow-control the remote, by the
‘
send special
character
’
commands. For out-of-band flow control, the transmitter optionally asserts RTS and
monitor CTS for permission to send; and assert/negate DTR when the Receive FIFO reaches a
user- definable threshold. Together, the in-band and out-of-band features not only allow the data
flow to be controlled in real time with minimum or no host intervention, it also prevents loss of
data.
As shown on the previous page, the CD1865 can interface virtually any CPU, with a minimum of
glue logic. Refer to the CD1865 Data Sheet for detailed information on how to interface various
microprocessors. Systems with multiple CD1865s are easily implemented, with no external glue,
by device a daisy-chain scheme. A
‘
fair share
’
feature ensures equal access for all service requests,
both within one CD1865 and across multiple devices.
FIFO
—
24 bytes of FIFO are dedicated to each channel partitioned as 8 bytes for transmitter,
8 bytes for receiver, and 8 bytes for status. The receive FIFO has a user-programmable threshold to
optimize system response and latency. The receive FIFO threshold programming range is from 1
–
8
characters.
Vectored Interrupt Structure
—
Three interrupt signals ([R, T, M]REQ*) are used. These signals
may also be read as an on-device register. Each REQ* signal represents one of three interrupt
groups: receive, transmit, and modem signal state changes. Upon servicing by the host, an interrupt
vector is generated by the CD1865 to define the interrupt group to be serviced and which CD1865
generated the interrupt. This allows the host software to enter directly into the proper interrupt
service routine, reducing the amount of interaction between the host and the controller, and
determining the nature of the interrupt.
Good Data Interrupt
—
If data received is all good, the host is advised of the number of good
data bytes in the FIFO, allowing the host to read data without further status queries until all good
data has been transferred.
Fair-Share Interrupt Scheme
—
To ensure equal service of all channels, a fair share scheme is
used for each interrupt group. No channel can interrupt for the same condition until all others have
a chance to be serviced for the same interrupt condition.
Typical CD1865 Host CPU Interface
CD1865 in Daisy-Chain Scheme
ADDRESS
DATA
CS*
DS*
R/W
DTACK*
ACKIN*
RREQ*
TREQ*
MREQ*
CD1865
CPU
INTERRUPT
CONTROLLER
ADDRESS
DECODE
AND
CLOGIC
TxD
RxD
DTR*
DSR*
RTS*
CTS*
CD*
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
Channel 0
CD1865
CD1865
CD1865
R
T
M
INTERRUPT
CONTROLLER
CPU
ACKIN* ACKOUT*
ACKIN* ACKOUT*
ACKIN* ACKOUT*
R
T
M
R
T
M
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相關(guān)代理商/技術(shù)參數(shù) |
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| CD1865N | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC |
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