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Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
129
Service Acknowledge Cycles are a special case of read cycles. The service acknowledge
‘
read
’
(which returns the Global Service Request Vector value to the host) is started when the read/write
state machine detects both DS* and another internal signal derived from both ACKIN* and DS*.
There are two possible worst-case paths to consider when determining whether DS* and ACKIN*
meet the necessary setup times to guarantee recognition on a particular clock edge. The longest
path is DS*; it must propagate through a gate, an 8-bit comparator, a state machine, and another
gate before arriving at the read/write state machine. The setup time for this is given in
Table 10
.
The other critical path is ACKIN*; it must pass through a state machine and a gate before arriving
at the read/write state machine. The setup time to guarantee recognition on a particular clock edge
is given in
Table 10
. Intel-style pin names are shown in {brackets}. All times are in nanoseconds,
unless otherwise specified.
Table 10. Clocked Timings
(Sheet 1 of 2)
Number in
Figures
Description
MIN (1)
MAX (1)
Notes
t
1
Setup, DS*{RD*} and CS* low to CLK low, for read or write cycle to start
(
‘
ordinary
’
reads and all writes)
10
2
t
2
Setup, DS* {RD*} low to CLK low, for service acknowledge cycle to start
(ACKIN* cycles and read cycles from acknowledge registers)
15
3
t
3
Setup, ACKIN* low to CLK low for cycle to start
10
t
4
Setup, Address valid to CS* and DS* low
3
t
5
Setup, Address valid to DS* (service acknowledge cycles)
4
4
t
6
Setup, Write Data valid to CLK high
0
t
7
Setup, R/W* {RD*, WR*} stable to DS* and CS* low (read, write cycles)
0
2
,
5
t
8
(DS* and CS*), or (RD* and CS*), or (WR* and CS*), high
5
6
,
7
t
9
Hold time, CS* low after CLK high (read, write cycles)
5
8
t
10
Hold time, DS* {RD*} after valid data
0
Infinity
8
t
11
Hold time, Address valid after CLK high
15
8
t
12
Hold time, Write Data valid after CLK high
10
t
13
Hold time, ACKIN* low after next CLK low
4
9
t
14
Clock Period (T
CLK
)
30
200
10
t
15
Clock low time
12
10
t
16
Clock high time
12
10
Clock duty cycle (50%
±
10%)
t
17
Clock rise/fall time
3
11
t
18
RESET pulse width (after power is good and clock is stable)
5 clock
periods
t
19
t
20
Data Bus out of Hi-Z after CLK low
0
12
Read Data valid after CLK high
35
t
21
t
22
ACKIN* to ACKOUT* propagation delay
12
ACKOUT* high after ACKIN* high
12
t
23
DS* {RD*} high to data bus three-state
0
10
t
24
DTACK* assert after CLK high (DTACKDLY = 0)
25
t
25
DTACK* assert after CLK low (DTACKDLY = 1)
20
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