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參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大小： | 200K |
| 代理商： | BX805565130P |
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Dual-Core Intel Xeon Processor 5100 Series Specification Update
17
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG9.
The Processor May Report a #TS Instead of a #GP Fault
Problem:
A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG10.
CS Limit Violation on RSM May be Serviced before Higher Priority
Interrupts/Exceptions
Problem:
When the processor encounters a CS (Code Segment) limit violation, a #GP (General
Protection Exception) fault is generated after all higher priority Interrupts and
exceptions are serviced. Because of this erratum, if RSM (Resume from System
Management Mode) returns to execution flow where a CS limit violation occurs, the
#GP fault may be serviced before a higher priority Interrupt or Exception (for example,
NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), and so
forth).
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG11.
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Problem:
With respect to the retirement of instructions, stores to the uncacheable memory-
based APIC register space are handled in a non-synchronized way. For example if an
instruction that masks the interrupt flag, for example, CLI, is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, that is, by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the
APIC register write. This will force the store to the APIC register before any subsequent
instructions are executed. No commercial operating system is known to be impacted by
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG12.
Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
Problem:
Software can enable DTS thermal interrupts by programming the thermal threshold
and setting the respective thermal interrupt enable bit. When programming DTS value,
the previous DTS threshold may be crossed. This will generate an unexpected thermal
interrupt.
Implication: Software may observe an unexpected thermal interrupt occur after reprogramming the
thermal threshold.
Workaround: In the ACPI/OS implement a workaround by temporarily disabling the DTS threshold
interrupt before updating the DTS threshold value.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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