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參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 200K |
| 代理商： | BX805565130P |
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Dual-Core Intel Xeon Processor 5100 Series Specification Update
19
AG17.
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
Problem:
An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)
to emulates real-address mode address wraparound at 1 megabyte. However, if all of
the following conditions are met, address bit 20 may not be masked.
Paging is enabled
A linear address has bit 20 set
The address references a large page
A20M# is enabled
Implication: When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been observed with
any commercially available operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address bit
20 could be applied to an address that references a large page. A20M# is normally only
used with the first megabyte of memory.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG18.
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
Problem:
Software which is written so that multiple agents can modify the same shared
unaligned memory location at the same time may experience a memory ordering issue
if multiple loads access this shared data shortly thereafter. Exposure to this problem
requires the use of a data write which spans a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not observed this
erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying shared
data by multiple agents:
The shared data is aligned
Proper semaphores or barriers are used in order to prevent concurrent data
accesses.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG19.
Code Segment limit violation may occur on 4-Gbyte limit check
Problem:
Code Segment limit violation may occur on 4-Gbyte limit check when the code stream
wraps around in a way that one instruction ends at the last byte of the segment and the
next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG20.
FP Inexact-Result Exception Flag May Not Be Set
Problem:
When the result of a floating-point operation is not exactly representable in the
destination format (1/3 in binary form, for example), an inexact-result (precision)
exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally
set by the processor. Under certain rare conditions, this bit may not be set when this
rounding occurs. However, other actions taken by the processor (invoking the software
exception handler if the exception is unmasked) are not affected. This erratum can only
occur if one of the following FST instructions is one or two instructions after the
floating-point operation which causes the precision exception:
FST m32real
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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