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參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 200K |
| 代理商： | BX805565130P |
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Dual-Core Intel Xeon Processor 5100 Series Specification Update
35
AG77.
Performance Monitoring Events for L1 and L2 Miss May Not be
Accurate
Problem:
Performance monitoring events 0CBh with an event mask value of 02h or 08h
(MEM_LOAD_RETIRED.L1_LINE_MISS or MEM_LOAD_RETIRED.L2_LINE_MISS) may
under count the cache miss events.
Implication: Performance monitoring events 0CBh with an event mask value of 02h or 08h may
show a count which is lower than expected; the amount by which the count is lower is
dependent on other conditions occurring on the same load that missed the cache.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG78.
A MOV Instruction from CR8 Register with 16 Bit Operand Size Will
Leave Bits 63:16 of the Destination Register Unmodified
Problem:
Moves to/from control registers are supposed to ignore REW.W and the 66H (operand
size) prefix. In systems supporting Intel Virtualization Technology, when the
processor is operating in VMX non-root operation and “use TPR shadow” VM-execution
control is set to 1, a MOV instruction from CR8 with a 16 bit operand size (REX.W =0
and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register
unmodified, instead of storing zeros in them.
Implication: Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG79.
Non-Temporal Data Store May be Observed in Wrong Program Order
Problem:
When non-temporal data is accessed by multiple read operations in one thread while
another thread performs a cacheable write operation to the same address, the data
stored may be observed in wrong program order (i.e. later load operations may read
older data).
Implication: Software that uses non-temporal data without proper serialization before accessing the
non-temporal data may observe data in wrong program order.
Workaround: : Software that conforms to the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 3A, section "Buffering of Write Combining Memory
Locations" will operate correctly
Status:
For the steppings affected, see the Summary Tables of Changes.
AG80.
Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Problem:
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track
retired SSE instructions. Due to this erratum, the processor may also count other types
of instructions resulting in higher than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than
expected.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG81.
VMCALL Failure due to Corrupt MSEG Location May Cause VM Exit to
Load the Machine State Incorrectly
Problem:
In systems supporting Intel VT, if a VMCALL failure occurs due to a corrupt Monitor
Segment (MSEG), subsequent VM Exits may load machine state incorrectly.
Implication: Occurrence of this erratum may result in a VMX abort.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
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| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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