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參數(shù)資料
| 型號(hào)： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 200K |
| 代理商： | BX805565130P |
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Dual-Core Intel Xeon Processor 5100 Series Specification Update
25
Implication: Early termination of REP CMPS/SCAS operation may be observed and RFLAGS may be
incorrectly updated.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG38.
FXSAVE/FXRSTOR Instructions which Store to the End of the Segment
and Cause a Wrap to a Misaligned Base Address (Alignment <=
0x10h) May Cause FPU Instruction or Operand Pointer Corruption
Problem:
If a FXSAVE/FXRSTOR instruction stores to the end of the segment causing a wrap to a
misaligned base address (alignment <= 0x10h), and one of the following conditions is
satisfied:
1) 32-bit addressing in 64-bit mode and address-size override is implemented
2) 16-bit addressing in legacy or compatibility mode
Then, depending on the wrap-around point, one of the below saved values may be
corrupted:
FPU Instruction Pointer Offset
FPU Instruction Pointer Selector
FPU Operand Pointer Selector
FPU Operand Pointer Offset
Implication: This erratum could cause FPU Instruction or Operand pointer corruption and may lead
to unexpected operations in the floating point exception handler.
Workaround: Avoid segment base mis-alignment and address wrap-around at the segment
boundary.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG39.
Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable System
Behavior
Problem:
When request for data from Core 1 results in a L1 cache miss, the request is sent to the
L2 cache. If this request hits a modified line in the L1 data cache of Core 2, certain
internal conditions may cause incorrect data to be returned to the Core 1.
Implication: This erratum may cause unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG40.
Software PREFETCHh Instruction Execution under Some Conditions
May Lead to Processor Livelock
Problem:
Software PREFETCHh instruction execution after a split load and dependent upon
ongoing store operations may lead to processor livelock.
Implication: Due to this erratum, the processor may livelock.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG41.
PREFETCHh Instructions May Not be Executed when Alignment Check
(AC) is Enabled
Problem:
PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may not be
executed when Alignment Check is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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