參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁(yè)數(shù)： 16/40頁(yè)
文件大?。?/td> 200K
代理商： BX805565130P
Dual-Core Intel Xeon Processor 5100 Series Specification Update
23
than once. After an amount of data greater than or equal to the address size structure
has been processed, external events (such as interrupts) will cause the (E)CX registers
to be increment by a value that corresponds to 64K bytes for 16 bit address size and
4G bytes for 32 bit address size.
Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or STOS
operations to re-execute. Intel has not observed this erratum with any commercially
available software.
Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than
the address space size (64K for 16-bit address size and 4G for 32-bit address size).
Status:
For the steppings affected, see the Summary Tables of Changes.
AG31.
Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
Problem:
The following events may be counted as instructions that contain a load by the
MEM_LOAD_RETIRED performance monitor events and may be counted as loads by the
INST_RETIRED (mask 01H) performance monitor event:
Prefetch instructions
x87 exceptions on FST* and FBSTP instructions
Breakpoint matches on loads, stores, and I/O instructions
Stores which update the A and D bits
Stores that split across a cache line
VMX transitions
Any instruction fetch that misses in the ITLB
Implication: The MEM_LOAD_RETIRED and INST_RETIRED (mask 01H) performance monitor events
may count a value higher than expected. The extent to which the values are higher
than expected is determined by the frequency of the above events.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG32.
Upper 32 bits of 'From' Address Reported through BTMs or BTSs May
be Incorrect
Problem:
When a far transfer switches the processor from 32-bit mode to IA-32e mode, the
upper 32 bits of the 'From' (source) addresses reported through the BTMs (Branch
Trace Messages) or BTSs (Branch Trace Stores) may be incorrect.
Implication: The upper 32 bits of the 'From' address debug information reported through BTMs or
BTSs may be incorrect during this transition
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG33.
Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
Problem:
The act of one processor, or system bus master, writing data into a currently executing
code segment of a second processor with the intent of having the second processor
execute that data as code is called cross-modifying code (XMC). XMC that does not
force the second processor to execute a synchronizing instruction, prior to execution of
the new code, is called unsynchronized XMC.
Software using unsynchronized XMC to modify the instruction byte stream of a
processor can see unexpected or unpredictable execution behavior from the processor
that is executing the modified code.
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