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參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 200K |
| 代理商： | BX805565130P |
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36
Dual-Core Intel Xeon Processor 5100 Series Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
AG82.
Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem:
The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the ENTER instruction results in a fault, the dynamic storage area of the
resultant stack frame may contain unexpected values (i.e. residual stack data as a
result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER
instruction. Please refer to "Procedure Calls For Block-Structured Languages" in IA-32
Intel Architecture Software Developer’s Manual, Vol. 1, Basic Architecture, for
information on the usage of the ENTER instructions. This erratum is not expected to
occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when
transferring to ring 0. Intel has not observed this erratum on any commercially
available software.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG83.
Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
Problem:
When data of Store to WT memory is used by two subsequent loads of one thread and
another thread performs cacheable write to the same address the first load may get the
data from external memory or L2 written by another core, while the second load will
get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Workaround: Do not use WB to WT aliasing.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG84.
VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed to
Cause VM Exit to Return to a Different Mode
Problem:
VMLAUNCH/VMRESUME instructions may not fail if the value of the “host address-space
size” VM-exit control differs from the setting of IA32_EFER.LMA.
Implication: Programming the VMCS to allow the monitor to be in different modes prior to
VMLAUNCH/VMRESUME and after VM-exit may result in undefined behavior
Workaround: Software should ensure that "host address-space size" VM-exit control has the same
value as IA32_EFER.LMA at the time of VMLAUNCH/VMRESUME.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG85.
IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem:
In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status:
For the steppings affected, see the Summary Tables of Changes.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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