參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 200K
代理商： BX805565130P
26
Dual-Core Intel Xeon Processor 5100 Series Specification Update
Implication: PREFETCHh instructions may not perform the data prefetch if Alignment Check is
enabled.
Workaround: Clear the AC flag (bit 18) in the EFLAGS register and/or the AM bit (bit 18) of Control
Register CR0 to disable alignment checking.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG42.
Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE
Memory Image May Be Unexpectedly All 1's after FXSAVE
Problem:
The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be set to all 1's
instead of the expected value of all 0's in the FXSAVE memory image if all of the
following conditions are true:
The processor is in 64-bit mode.
The last floating point operation was in compatibility mode
Bit 31 of the FPU Data (Operand) Pointer is set.
An FXSAVE instruction is executed
Implication: Software depending on the full FPU Data (Operand) Pointer may behave unpredictably.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG43.
Concurrent Multi-processor Writes to Non-dirty Page May Result in
Unpredictable Behavior
Problem:
When a logical processor writes to a non-dirty page, and another logical-processor
either writes to the same non-dirty page or explicitly sets the dirty bit in the
corresponding page table entry, complex interaction with internal processor activity
may cause unpredictable system behavior.
Implication: This erratum may result in unpredictable system behavior and hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG44.
Performance Monitor IDLE_DURING_DIV (18h) Count May Not be
Accurate
Problem:
Performance monitoring events that count the number of cycles the divider is busy and
no other execution unit operation or load operation is in progress may not be accurate.
Implication: The counter may reflect a value higher or lower than the actual number of events.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG45.
Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
Problem:
After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their
data invalid. The corresponding data if sent out as a BTM on the system bus will also be
incorrect.
Note: This issue would only occur when one of the 3 above mentioned debug support
facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be
used.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
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