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參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大小： | 200K |
| 代理商： | BX805565130P |
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22
Dual-Core Intel Xeon Processor 5100 Series Specification Update
1) If an instruction that performs a memory load causes a code segment limit violation
2) If a waiting floating-point instruction or MMX instruction that performs a memory
load has a floating-point exception pending
3) If an MMX or SSE instruction that performs a memory load and has either CR0.EM=1
(Emulation bit set), or a floating-point Top-of-Stack (FP TOS) not equal to 0, or a DNA
exception pending
Implication: In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, nor from the
restart and subsequent re-execution of that instruction by the exception handler. If the
target of the load is to uncached memory that has a system side-effect, restarting the
instruction may cause unexpected system behavior due to the repetition of the side-
effect.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG27.
General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
Problem:
In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that
occur above the 4G limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP
fault.
Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the
4G limit (0ffffffffh).
Status:
For the steppings affected, see the Summary Tables of Changes.
AG28.
EIP May be Incorrect after Shutdown in IA-32e Mode
Problem:
When the processor is going into shutdown state the upper 32 bits of the instruction
pointer may be incorrect. This may be observed if the processor is taken out of
shutdown state by NMI#.
Implication: A processor that has been taken out of the shutdown state may have an incorrect EIP.
The only software which would be affected is diagnostic software that relies on a valid
EIP.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG29.
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable (XD) is Not Supported
Problem:
A #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor
which does not support Execute Disable (XD) functionality.
Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG30.
(E)CX May Get Incorrectly Updated When Performing Fast String REP
MOVS or Fast String REP STOS With Large Data Structures
Problem:
When performing Fast String REP MOVS or REP STOS commands with data structures
[(E)CX*Data Size] larger than the supported address size structure (64K for 16-bit
address size and 4G for 32-bit address size) some addresses may be processed more
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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