- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223478 > BX805565130P (INTEL CORP) 64-BIT, MICROPROCESSOR, BGA771 PDF資料下載
參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 24/40頁 |
| 文件大小： | 200K |
| 代理商： | BX805565130P |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
30
Dual-Core Intel Xeon Processor 5100 Series Specification Update
AG59.
AE4. REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types may use
an Incorrect Data Size or Lead to Memory-Ordering Violations.
Problem:
Under certain conditions as described in the Software Developers Manual section “Out-
of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or may observe memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new page
memory type:
UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG60.
MOV To/From Debug Registers Causes Debug Exception
Problem:
When in V86 mode, if a MOV instruction is executed on to/from a debug registers, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
did occur in V86 mode, the exception may be directed to the general-protection
exception handler.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG61.
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
Problem:
This erratum may occur when the Pentium III processor executes one of the following
read-modify-write arithmetic instructions and a page fault occurs during the store of
the memory operand: ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR,
ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD. In this case, the
EFLAGS value pushed onto the stack of the page fault handler may reflect the status of
the register after the instruction would have completed execution rather than before it.
The following conditions are required for the store to generate a page fault and call the
operating system page fault handler:
1. The store address entry must be evicted from the DTLB by speculative loads
from other instructions that hit the same way of the DTLB before the store has
completed. DTLB eviction requires at least three-load operations that have linear
address bits 15:12 equal to each other and address bits 31:16 different from each
other in close physical proximity to the arithmetic operation.
2. The page table entry for the store address must have its permissions tightened
during the very small window of time between the DTLB eviction and execution of
相關PDF資料 |
PDF描述 |
|---|---|
| BX805573060 | 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775 |
| BX80562X3210SLACU | 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775 |
| BX80616I5660SLBLV | 64-BIT, 133 MHz, MICROPROCESSOR, PBGA1156 |
| BXA10-48D15-S | DC to DC Converter |
| BXA10-48S05 | EMI FILTER INCLUDING ESD PROTECTION |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。