- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223478 > BX805565130P (INTEL CORP) 64-BIT, MICROPROCESSOR, BGA771 PDF資料下載
參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 200K |
| 代理商： | BX805565130P |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Dual-Core Intel Xeon Processor 5100 Series Specification Update
15
Errata
AG1.
Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem:
If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set.
If there is no Interrupt
Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does
not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service
register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG2.
LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
Problem:
During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is
received during a snoop phase and the Locked transaction is pipelined on the front side
bus (FSB), LOCK# may unexpectedly de-assert.
Implication: When this erratum occurs, the system may hang during shutdown. Intel has not
observed this erratum with any commercially available systems or software.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG3.
Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
Problem:
When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in
the MCA address register (MCi_ADDR). Under some scenarios, the address reported
may be incorrect.
Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC
errors.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG4.
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
Problem:
The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF)
is zero after executing the following instructions
1) VERR (ZF=0 indicates unsuccessful segment read verification)
2) VERW (ZF=0 indicates unsuccessful segment write verification)
3) LAR (ZF=0 indicates unsuccessful access rights load)
4) LSL (ZF=0 indicates unsuccessful segment limit load)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BX805573060 | 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775 |
| BX80562X3210SLACU | 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775 |
| BX80616I5660SLBLV | 64-BIT, 133 MHz, MICROPROCESSOR, PBGA1156 |
| BXA10-48D15-S | DC to DC Converter |
| BXA10-48S05 | EMI FILTER INCLUDING ESD PROTECTION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。