參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁數(shù)： 2/40頁
文件大?。?/td> 200K
代理商： BX805565130P
10
Dual-Core Intel Xeon Processor 5100 Series Specification Update
AG25
X
No Fix
Power Cycle Generator Bus Transactions Will Not Be Counted As Local
Transactions
AG26
X
No Fix
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AG27
X
No Fix
General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
AG28
X
No Fix
EIP May be Incorrect after Shutdown in IA-32e Mode
AG29
X
No Fix
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When
Execute Disable (XD) is Not Supported
AG30
X
Plan Fix
(E)CX May Get Incorrectly Updated When Performing Fast String REP
MOVS or Fast String REP STOS With Large Data Structures
AG31
X
Plan Fix
Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
AG32
X
No Fix
Upper 32 bits of 'From' Address Reported through BTMs or BTSs May
be Incorrect
AG33
X
No Fix
Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
AG34
X
No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AG35
X
No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AG36
X
No Fix
Split Locked Stores May not Trigger the Monitoring Hardware
AG37
X
No Fix
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when
RCX >= 0X100000000
AG38
X
Plan Fix
FXSAVE/FXRSTOR Instructions which Store to the End of the Segment
and Cause a Wrap to a Misaligned Base Address (Alignment <=
0x10h) May Cause FPU Instruction or Operand Pointer Corruption
AG39
X
Plan Fix
Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable System
Behavior
AG40
X
Plan Fix
Software PREFETCHh Instruction Execution under Some Conditions
May Lead to Processor Livelock
AG41
X
Plan Fix
PREFETCHh Instructions May Not be Executed when Alignment Check
(AC) is Enabled
AG42
X
Plan Fix
Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE
Memory Image May Be Unexpectedly All 1's after FXSAVE
AG43
X
Plan Fix
Concurrent Multi-processor Writes to Non-dirty Page May Result in
Unpredictable Behavior
AG44
X
Plan Fix
Performance Monitor IDLE_DURING_DIV (18h) Count May Not be
Accurate
AG45
X
No Fix
Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AG46
X
No Fix
Shutdown May Disable Non-Bootstrap Processors
AG47
X
Plan Fix
SYSCALL Immediately after Changing EFLAGS.TF May Not Behave
According to the New EFLAGS.TF
AG48
X
No Fix
Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions
AG49
X
No Fix
VM Bit is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
Errata (Sheet 2 of 4)
Number
Steppings
Status
ERRATA
B-2
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