參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁(yè)數(shù)： 8/40頁(yè)
文件大?。?/td> 200K
代理商： BX805565130P
16
Dual-Core Intel Xeon Processor 5100 Series Specification Update
Implication: The value of the LER MSR may be inaccurate if VERW/VERR/LSL/LAR instructions are
executed after the occurrence of an exception.
Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR
before executing VERW/VERR/LSL/LAR instructions.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG5.
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
Problem:
Performance monitoring for Event CFH normally increments on saturating SIMD
instruction retired. Regardless of DR7 programming, if the linear address of a retiring
memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the CFH counter may be incorrectly incremented.
Implication: The value observed for performance monitoring count for saturating SIMD instructions
retired may be too high. The size of the error is dependent on the number of
occurrences of the conditions described above, while the counter is active.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG6.
SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
Problem:
In normal operation, SYSRET will restore the value of RFLAGS from R11 (the value
previously saved upon execution of the SYSCALL instruction). Due to this erratum, the
RFLAGS.RF bit will be unconditionally cleared after execution of the SYSRET instruction.
Implication: The SYSRET instruction can not be used if the RF flag needs to be set after returning
from a system call. Intel has not observed this erratum with any commercially available
software.
Workaround: Use the IRET instruction to return from a system call, if RF flag has to be set after the
return.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG7.
General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted
Problem:
When the processor encounters an instruction that is greater than 15 bytes in length, a
#GP is signaled when the instruction is decoded. Under some circumstances, the #GP
fault may be preempted by another lower priority fault (for example, Page Fault (#PF)).
However, if the preempting lower priority faults are resolved by the operating system
and the instruction retried, a #GP fault will occur.
Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault.
Instructions of greater than 15 bytes in length can only occur if redundant prefixes are
placed before the instruction.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG8.
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
Problem:
Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag)
instruction are serviced immediately after the STI instruction is executed. Because of
this erratum, if following STI, an instruction that triggers a #MF is executed while
STPCLK#, Enhanced Intel SpeedStep Technology transitions or Thermal Monitor 1
events occur, the pending #MF may be serviced before higher priority interrupts.
Implication: Software may observe #MF being serviced before higher priority interrupts.
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