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參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 200K |
| 代理商： | BX805565130P |
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20
Dual-Core Intel Xeon Processor 5100 Series Specification Update
FST m64real
FSTP m32real
FSTP m64real
FSTP m80real
FIST m16int
FIST m32int
FISTP m16int
FISTP m32int
FISTP m64int
FISTTP m16int
FISTTP m32int
FISTTP m64int
Note that even if this combination of instructions is encountered, there is also a
dependency on the internal pipelining and execution state of both instructions in the
processor.
Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it
happens frequently, and produces a rounded result acceptable to most applications.
The PE bit of the FPU status word may not always be set upon receiving an inexact-
result exception. Thus, if these exceptions are unmasked, a floating-point error
exception handler may not recognize that a precision exception occurred. Note that this
is a "sticky" bit, that is, once set by an inexact-result condition, it remains set until
cleared by software.
Workaround: This condition can be avoided by inserting three non-floating-point instructions
between the two floating-point instructions.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG21.
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM instruction before Restoring the Architectural
State from SMRAM
Problem:
The Resume from System Management Mode (RSM) instruction does not flush global
pages from the Data Translation Look-Aside Buffer (DTLB) prior to reloading the saved
architectural state.
Implication: If SMM turns on paging with global paging enabled and then maps any of linear
addresses of SMRAM using global pages, RSM load may load data from the wrong
location.
Workaround: Do not use global pages in system management mode.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG22.
Sequential Code Fetch to Non-canonical Address May have Non-
deterministic Results
Problem:
If code sequentially executes off the end of the positive canonical address space (falling
through from address 00007fffffffffff to non- canonical address 0000800000000000),
under some circumstances the code fetch will be converted to a canonical fetch at
address ffff800000000000.
Implication: Due to this erratum, the processor may transfer control to an unintended address. The
result of fetching code at that address is unpredictable and may include an unexpected
trap or fault, or execution of the instructions found there.
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相關(guān)代理商/技術(shù)參數(shù) |
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| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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