
Dual-Core Intel Xeon Processor 5100 Series Specification Update
33
AG69.
PEBS Buffer Overflow Status Will Not be Indicated Unless
IA32_DEBUGCTL[12] is Set
Problem:
IA32_PERF_GLOBAL_STATUS MSR (38EH) bit [62] when set, indicates that a PEBS
(Precise Event-Based Sampling) overflow has occurred and a PMI (Performance Monitor
Interrupt) has been sent. Due to this erratum, this bit will not be set unless
IA32_DEBUGCTL MSR (1D9H) bit [12] (which stops all Performance Monitor Counters
upon a PMI) is also set.
Implication: Unless IA32_DEBUGCTL[12] is set, IA32_PERF_GLOBAL_STATUS[62] will not indicate
that a PMI was generated due to a PEBS Overflow.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG70.
The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
Problem:
DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8)
of the EFLAGS Register is set, and a #DB (Debug Exception) occurs due to one of the
following:
DR7 GD (General Detect, bit 13) being bit set;
INT1 instruction;
Code breakpoint.
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified
Status:
For the steppings affected, see the Summary Tables of Changes.
AG71.
An Asynchronous MCE During a Far Transfer May Corrupt ESP
Problem:
If an asynchronous machine check occurs during an interrupt, call through gate, FAR
RET or IRET and in the presence of certain internal conditions, ESP may be corrupted.
Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a
triple fault will occur due to the corrupted stack pointer, resulting in a processor
shutdown. If the MCE is called with a stack switch, e.g. when the CPL (Current Privilege
Level) was changed or when going through an interrupt task gate, then the corrupted
ESP will be saved on the new stack or in the TSS (Task State Segment), and will not be
used.
Workaround: Use an interrupt task gate for the machine check handler.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG72.
In Single-Stepping on Branches Mode, the BS Bit in the Pending-
Debug-Exceptions Field of the Guest State Area will be Incorrectly Set
by VM Exit on a MOV to CR8 Instruction
Problem:
In a system supporting Intel Virtualization Technology, the BS bit (single step bit 14
of the Pending-Debug-Exceptions field) in the guest state area will be incorrectly set
when all of the following conditions occur:
The processor is running in VMX non-root as a 64 bit mode guest;
The “CR8-load exiting” VM-execution control is 0 and the “use TPR shadow” VM-
execution is 1;
Both BTF (Single-Step On Branches, bit 1) of the IA32_DEBUGCTL MSR (1D9H)
Register and the TF (Trap Flag, bit 8) of the RFLAGS Register are set;
“MOV CR8, reg” attempts to program a TPR (Task Priority Register) value that is
below the TPR threshold and causes a VM exit.
Implication: A Virtual-Machine Monitor will sample the BS bit and will incorrectly inject a Single-Step
trap to the guest.