參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁(yè)數(shù)： 3/40頁(yè)
文件大?。?/td> 200K
代理商： BX805565130P
Dual-Core Intel Xeon Processor 5100 Series Specification Update
11
AG50
X
Plan Fix
IA32_FMASK is Reset during an INIT
AG51
X
No Fix
Code Breakpoint May Be Taken after POP SS Instruction if it is
followed by an Instruction that Faults
AG52
X
No Fix
Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
AG53
X
No Fix
IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
AG54
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AG55
X
Plan Fix
Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
AG56
X
Plan Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
AG57
X
No Fix
BTS Message May Be Lost When the STPCLK# Signal is Active.
AG58
X
No Fix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
to 248 May Terminate Early
AG59
X
No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
AG60
X
No Fix
MOV To/From Debug Registers Causes Debug Exception
AG61
X
No Fix
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
AG62
X
No Fix
LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
AG63
X
No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
AG64
X
No Fix
A Thermal Interrupt is Not Generated when the Current Temperature
is Invalid
AG65
X
No Fix
No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AG66
X
Plan Fix
Plan Fix CPL-Qualified BTS May Report Incorrect Branch-From
Instruction Address
AG67
X
Plan Fix
Plan Fix PEBS Does Not Always Differentiate Between CPL-Qualified
Events
AG68
X
No Fix
No Fix PMI May be Delayed to Next PEBS Event
AG69
X
No Fix
A PEBS Buffer Overflow Status Will Not be Indicated Unless
IA32_DEBUGCTL[12] is Set
AG70
X
Plan Fix
The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
AG71
X
No Fix
An Asynchronous MCE During a Far Transfer May Corrupt ESP
AG72
X
Plan Fix
In Single-Stepping on Branches Mode, the BS Bit in the Pending-
Debug-Exceptions Field of the Guest State Area will be Incorrectly Set
by VM-Exit on a MOV to CR8 Instruction
AG73
X
Plan Fix
B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
AG74
X
No Fix
VM Exit due to Virtual APIC-Access May Clear RF
AG75
X
No Fix
BTM/BTS Branch-From Instruction Address May be Incorrect for
Software Interrupts
AG76
X
Plan Fix
REP Store Instructions in a Specific Situation may cause the Processor
to Hang
Errata (Sheet 3 of 4)
Number
Steppings
Status
ERRATA
B-2
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