參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁數(shù)： 40/40頁
文件大?。?/td> 200K
代理商： BX805565130P
Dual-Core Intel Xeon Processor 5100 Series Specification Update
9
Errata (Sheet 1 of 4)
Number
Steppings
Status
ERRATA
B-2
AG1
X
No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May
Cause an Unexpected Interrupt
AG2
X
No Fix
LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
AG3
X
No Fix
Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
AG4
X
No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
AG5
X
No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
AG6
X
Plan Fix
SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
AG7
X
No Fix
General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted
AG8
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
AG9
X
No Fix
The Processor May Report a #TS Instead of a #GP Fault
AG10
X
No Fix
CS Limit Violation on RSM May be Serviced before Higher Priority
Interrupts/Exceptions
AG11
X
No Fix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AG12
X
No Fix
Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
AG13
X
No Fix
Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
May be Incorrect
AG14
X
No Fix
Last Exception Record (LER) MSRs May be Incorrectly Updated
AG15
X
No Fix
Performance Monitoring Events for Retired Instructions (C0H) May Not
Be Accurate
AG16
X
No Fix
Performance Monitoring Event For Number Of Reference Cycles When
The Processor Is Not Halted (3CH) Does Not Count According To The
Specification
AG17
X
No Fix
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
AG18
X
No Fix
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
AG19
X
No Fix
Code Segment limit violation may occur on 4-Gbyte limit check
AG20
X
Plan Fix
FP Inexact-Result Exception Flag May Not Be Set
AG21
X
Plan Fix
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM instruction before Restoring the Architectural
State from SMRAM
AG22
X
Plan Fix
Sequential Code Fetch to Non-canonical Address May have Non-
deterministic Results
AG23
X
Plan Fix
VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores
Reserved Bit settings in VM-exit Control Field
AG24
X
No Fix
The PECI Controller Resets to the Idle State
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