參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁(yè)數(shù)： 21/40頁(yè)
文件大小： 200K
代理商： BX805565130P
28
Dual-Core Intel Xeon Processor 5100 Series Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
AG51.
Code Breakpoint May Be Taken after POP SS Instruction if it is
followed by an Instruction that Faults
Problem:
A POP SS instruction should inhibit all interrupts including Code Breakpoints until after
execution of the following instruction. This allows sequential execution of POP SS and
MOV eSP, eBP instructions without having an invalid stack during interrupt handling.
However, a code breakpoint may be taken after POP SS if it is followed by an
instruction that faults, this results in a code breakpoint being reported on an
unexpected instruction boundary since both instructions should be atomic.
Implication: This can result in a mismatched Stack Segment and SP. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: As recommended in the IA32 Intel Architecture Software Developer's Manual, the use
"POP SS" in conjunction with "MOV eSP, eBP" will avoid the failure since the "MOV" will
not fault.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG52.
Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
Problem:
A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to
the LBR_TO value.
Implication: The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG53.
IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
Problem:
The IO_SMI bit in SMRAM's location 7FA4H is set to "1" by the CPU to indicate a System
Management Interrupt (SMI) occurred as the result of executing an instruction that
reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by:
A non-I/O instruction.
SMI is pending while a lower priority event interrupts
A REP I/O read
An I/O read that redirects to MWAIT
In systems supporting Intel Virtualization Technology a fault in the middle of an
IO operation that causes a VM Exit
Implication: SMM handlers may get false IO_SMI indication.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM handler must not
restart an I/O instruction if the platform has not been configured to generate a
synchronous SMI for the recorded I/O port address.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG54.
INIT Does Not Clear Global Entries in the TLB
Problem:
INIT may not flush a TLB entry when:
The processor is in protected mode with paging enabled and the page global enable
flag is set (PGE bit of CR4 register)
G bit for the page table entry is set
TLB entry is present in TLB when INIT occurs
Implication: Software may encounter unexpected page fault or incorrect address translation due to
a TLB entry erroneously left in TLB after INIT.
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