參數資料
型號： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁數： 28/40頁
文件大?。?/td> 200K
代理商： BX805565130P
34
Dual-Core Intel Xeon Processor 5100 Series Specification Update
Workaround: A Virtual-Machine Monitor must manually disregard the BS bit in the Guest State Area
in case of a VM exit due to a TPR value below the TPR threshold.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG73.
B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
Problem:
B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly
cleared when the following sequence happens:
1. POP instruction to SS (Stack Segment) selector;
2. Next instruction is FP (Floating Point) that gets FP assist followed by code
breakpoint.
Implication: B0-B3 bits in DR6 may be set incorrectly not be properly cleared.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG74.
VM Exit due to Virtual APIC-Access May Clear RF
Problem:
RF (Resume Flag), bit 16 of the EFLAGS/RFLAGS register, is used to restart instruction
execution without getting an instruction breakpoint on the instruction following a
debug breakpoint exception. Due to this erratum, in a system supporting Intel
Virtualization Technology, when a VM Exit occurs due to Virtual APIC-Access (Advanced
Programmable Interrupt Controller-Access) the EFLAGS/RFLAGS saved in the VMCS
(Virtual-Machine Control Structure) may contain an RF value of 0.
Implication: When this erratum occurs, following a VM Exit due to a Virtual APIC-access, the
processor may unintentionally break on the subsequent instruction after VM entry.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG75.
BTM/BTS Branch-From Instruction Address May be Incorrect for
Software Interrupts.
Problem:
When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software
interrupt may result in the overwriting of BTM/BTS branch-from instruction address by
the LBR (Last Branch Record) branch-from instruction address.
Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG76.
REP Store Instructions in a Specific Situation may cause the Processor
to Hang
Problem:
During a series of REP (repeat) store instructions a store may try to dispatch to
memory prior to the actual completion of the instruction. This behavior depends on the
execution order of the instructions, the timing of a speculative jump and the timing of
an uncacheable memory store. All types of REP store instructions are affected by this
erratum
Implication: When this erratum occurs, the processor may live lock and/or result in a system hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
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參數描述
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BX805565160A S L9RT 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box
BX805565160A S LABS 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box
BX805565160P S LAG9 制造商:Intel 功能描述:
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