參數(shù)資料
型號(hào)： AM54BDS128AGT89IT
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 10 X 10 MM, 0.80 PITCH, FBGA-93
文件頁(yè)數(shù)： 8/71頁(yè)
文件大小： 1031K
代理商： AM54BDS128AGT89IT
July 23, 2002
Am54BDS128AG
16
ADV ANCE
I N FO RMAT I O N
not be at V
ID for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
When at V
IL, ACC locks all sectors. ACC should be at
V
IH for all other conditions.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Autoselect mode may only be entered
and used when in the asynchronous read mode. Refer
page 27 section for more information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at V
CC ± 0.2 V.
The device requires standard access time (t
CE) for
read access, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the opera-
tion is completed.
I
CC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. While in asynchronous mode, the
device automatically enables this mode when ad-
dresses remain stable for t
ACC + 60 ns. The automatic
sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings pro-
vide new data when addresses are changed. While in
sleep mode, output data is latched and always avail-
able to the system. While in synchronous mode, the
device automatically enables this mode when either
the first active CLK edge occurs after t
ACC or the CLK
runs slower than 5MHz. Note that a new burst opera-
tion is required to provide new data.
I
37 represents the automatic sleep mode current spec-
ification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of re-
setting the device to reading array data. When RE-
SET# is driven low for at least a period of t
RP, the
device immediately terminates any operation in
progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS ± 0.2 V, the de-
vice draws CMOS standby current (I
CC4). If RESET# is
held at V
IL but not within VSS ± 0.2 V, the standby cur-
rent will be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the device requires a time of t
READY (during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a pro-
gram or erase operation is not executing, the reset op-
eration is completed within a time of t
READY (not during
Embedded Algorithms). The system can read data t
RH
after RESET# returns to V
IH.
Refer to the AC Characteristics tables for RESET# pa-
page 50 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH, output from the device is
disabled. The outputs are placed in the high imped-
ance state.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 13, “Com-
tions).
The device offers two types of data protection at the
sector level:
s The sector lock/unlock command sequence dis-
ables or re-enables both program and erase opera-
tions in any sector.
s When WP# is at V
IL, sectors 0 and 1 (bottom boot)
or sectors 132 and 133 (top boot) are locked.
s When ACC is at V
IL, all sectors are locked.
The following hardware data protection measures pre-
vent accidental erasure or programming, which might
otherwise be caused by spurious system level signals
相關(guān)PDF資料
PDF描述
AM7200-65RC 256 X 9 OTHER FIFO, 65 ns, PDIP28
AM7200-80RC 256 X 9 OTHER FIFO, 80 ns, PDIP28
AM7201-25DC 512 X 9 OTHER FIFO, 25 ns, CDIP28
AM7203-65JC 2K X 9 OTHER FIFO, 65 ns, PQCC32
AM7831X DUAL LINE DRIVER, UUC16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM54S 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Four-Bit Shifter With Three-State Outputs
AM54S350 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Four-Bit Shifter With Three-State Outputs
AM-55 制造商:Amprobe Test Tools 功能描述:Digital Multimeter
AM-550 功能描述:數(shù)字萬(wàn)用表 Digital Multimeter TRMS RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類(lèi)型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持:
AM55-0001 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:140 mW Power Amplifier with T/R and Diversity Switches 2.42.5 GHz
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*