參數(shù)資料
型號(hào)： AM54BDS128AGT89IT
廠商： ADVANCED MICRO DEVICES INC
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 10 X 10 MM, 0.80 PITCH, FBGA-93
文件頁(yè)數(shù)： 62/71頁(yè)
文件大?。?/td> 1031K
代理商： AM54BDS128AGT89IT
65
Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
CW is measured from CE1#s going low to the end of write.
3. t
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. t
AS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP is measured from the beginning of write
to the end of write.
Figure 36.
SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
78, 79
88, 89
Unit
t
WC
Write Cycle Time
Min
70
85
ns
t
Cw
Chip Enable to End of Write
Min
60
70
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
60
70
ns
t
BW
UB#s, LB#s to End of Write
Min
60
70
ns
t
WP
Write Pulse Time
Min
50
60
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
ns
Max
20
t
DW
Data to Write Time Overlap
Min
30
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
min
5
ns
Address
CS1#s
UB#s, LB#s
WE#
Data In
Data Out
tWC
tCW
(See Note 2)
tAW
High-Z
Data Valid
CS2s
tCW
(See Note 2)
tBW
tWP
(See Note 5)
tAS
(See Note 4)
tWR (See Note 3)
tWHZ
tDW
tDH
tOW
(See Note 9)
(See Note 7)
(See Note 6)
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