參數(shù)資料
型號： AM54BDS128AGT89IT
廠商： ADVANCED MICRO DEVICES INC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 10 X 10 MM, 0.80 PITCH, FBGA-93
文件頁數(shù)： 2/71頁
文件大?。?/td> 1031K
代理商： AM54BDS128AGT89IT
July 23, 2002
Am54BDS128AG
10
ADV ANCE
I N FO RMAT I O N
PIN DESCRIPTION
A19–A0
= 20 Address Inputs (Common)
A21–A20
= 2 Address Inputs (Flash)
DQ15–DQ0 = 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash)
CE#f2
= Chip Enable 2 (Flash)
CE1#s
= Chip Enable 1 (SRAM)
CE2s
= Chip Enable 2 (SRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
UB#s
= Upper Byte Control (SRAM)
LB#s
= Lower Byte Control (SRAM)
RESET#
= Hardware Reset Pin, Active Low
V
CCf
= Flash 1.8 volt-only single power
supply (see Product Selector Guide
for speed options and voltage supply
tolerances)
V
IOf
= Input & Output Buffer Power Supply
must be tied to V
CCf.
V
CCs
= SRAM Power Supply
V
SSIOf
= Output Buffer Ground
V
SS
= Device Ground (Common)
NC
= Pin Not Connected Internally
RDY
= Ready output; indicates the status of
the Burst read. Low = data not valid at
expected time. High = data valid.
CLK
= CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
AVD#
= Address Valid input. Indicates to de-
vice that the valid address is present
on the address inputs (A21–A0).
Low = for asynchronous mode, indi-
cates valid address; for burst mode,
causes starting address to be latched.
High = device ignores address inputs
WP#
= Hardware write protect input. At V
IL,
disables program and erase functions
in the two outermost sectors. Should
be at V
IH for all other conditions.
ACC
= At V
ID, accelerates programming; au-
tomatically places device in unlock by-
pass mode. At V
IL, locks all sectors.
Should be at V
IH for all other condi-
tions.
FLASH LOGIC SYMBOL
20
16
DQ15–DQ0
A19–A0
CE#f1
OE#
WE#
RESET#
UB#s
RDY
WP#
A21–A20
LB#s
ACC
CE1#s
CE2s
AVD#
CLK
CE#f2
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