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參數(shù)資料
| 型號： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁數(shù)： | 7/71頁 |
| 文件大?。?/td> | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
but wraps back to the first address in the selected
group. In a similar fashion, the 16-word and 32-word
Linear Wrap modes begin their burst sequence on the
starting address written to the device, and then wrap
back to the first address in the selected address
group. Note that in these three burst read modes
the address pointer does not cross the boundary
that occurs every 64 words; thus, no wait states
are inserted (except during the initial access).
The RDY pin indicates when data is valid on the bus.
The devices can wrap through a maximum of 128
words of data (8 words up to 16 times, 16 words up to
8 times, or 32 words up to 4 times) before requiring a
new synchronous access (latching of a new address).
Burst Mode Configuration Register
The device uses a configuration register to set the var-
ious burst parameters: number of wait states, burst
read mode, active clock edge, RDY configuration, and
synchronous mode active.
Handshaking Option
The device is equipped with a handshaking feature
that allows the host system to simply monitor the RDY
signal from the device to determine when the initial
word of burst data is ready to be read. The host sys-
tem should use the programmable wait state configu-
ration to set the number of wait states for optimal burst
mode operation. The initial word of burst data is indi-
cated by the rising edge of RDY after OE# goes low.
The presence of the handshaking feature may be veri-
fied by writing the autoselect command sequence to
the device. See “Autoselect Command Sequence” for
details.
For optimal burst mode performance on devices with-
out the handshaking option, the host system must set
the appropriate number of wait states in the flash de-
vice depending on clock frequency and the presence
of a boundary crossing. See “Set Burst Mode Configu-
24 section for more information. The device will auto-
matically delay RDY and data by one additional clock
cycle when the starting address is odd.
The autoselect function allows the host system to de-
termine whether the flash device is enabled for hand-
shaking. See the “Autoselect Command Sequence”
section for more information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in another
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same ba nk (except the sector b ein g
Timings,” on page 62 shows how read and write cy-
cles may be initiated for simultaneous operation with
zero latency. Refer to the DC Characteristics table for
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asyn-
chronous or synchronous write operation. During a
synchronous write operation, to write a command or
command sequence (which includes programming
data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to V
IL, and OE# to
V
IH when providing an address to the device, and drive
WE# and CE# to V
IL, and OE# to VIH. when writing
commands or data. During an asynchronous write op-
eration, the system must drive CE# and WE# to V
IL
and OE# to V
IH when providing an address, command,
and data. The asynchronous and synchronous pro-
graming operation is independent of the Set Device
Read Mode bit in the Burst Mode Configuration Regis-
ter.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 8, “Programmable
Wait State Settings,” on page 25 indicates the address
space that each sector occupies. The device address
space is divided into four banks: Banks B and C con-
tain only 32 Kword sectors, while Banks A and D con-
tain both 8 Kword boot sectors in addition to 32 Kword
sectors. A “bank address” is the address bits required
to uniquely select a bank. Similarly, a “sector address”
is the address bits required to uniquely select a sector.
I
CC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. ACC is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts V
ID on this input, the device auto-
matically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the input to re-
duce the time required for program operations. The
system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Re-
moving V
ID from the ACC input returns the device to
normal operation. Note that sectors must be unlocked
prior to raising ACC to V
ID. Note that the ACC pin must
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