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| 型號(hào)： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁(yè)數(shù)： | 50/71頁(yè) |
| 文件大小： | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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July 23, 2002
Am54BDS128AG
54
ADV ANCE
I N FO RMAT I O N
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration
Register.
7. CLK must not have an active edge while WE# is at V
IL.
8. AVD# must toggle during command sequence unlock cycles.
9. CE#f refers to active flash die.
Figure 23.
Synchronous Program Operation Timings
OE#
CE#f
Data
Addresses
AVD#
WE#
CLK
VCC
555h
PD
tAS
tWP
tAH
tWC
tWPH
PA
tVCS
tDH
tCH
In
Progress
tWHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
tDS
tAVDP
A0h
tAHW
tACS
tCAS
tACH
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