參數(shù)資料
型號(hào)： AM54BDS128AGT89IT
廠商： ADVANCED MICRO DEVICES INC
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 10 X 10 MM, 0.80 PITCH, FBGA-93
文件頁(yè)數(shù)： 6/71頁(yè)
文件大?。?/td> 1031K
代理商： AM54BDS128AGT89IT
July 23, 2002
Am54BDS128AG
14
ADV ANCE
I N FO RMAT I O N
FLASH DEVICE BUS OPERATIONS
Requirements for Asynchronous Read
Operation (Non-Burst)
To read data from the memory array, the system must
first assert a valid address on A21–A0, while driving
AVD# and CE# to V
IL. WE# should remain at VIH. The
rising edge of AVD# latches the address. The data will
appear on DQ15–DQ0. Since the memory array is di-
vided into four banks, each bank remains enabled for
read access until the command register contents are
altered.
Address access time (t
ACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE ) is the delay from the stable ad-
dresses and stable CE# to valid data at the outputs.
The output enable access time (t
OE) is the delay from
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition.
Requirements for Synchronous (Burst)
Read Operation
The device is capable of continuous sequential burst
operation and linear burst operation of a preset length.
When the device first powers up, it is enabled for
asynchronous read operation.
Prior to entering burst mode, the system should deter-
mine how many wait states are desired for the initial
word (t
IACC) of each burst access, what mode of burst
operation is desired, which edge of the clock will be
the active clock edge, and how the RDY signal will
transition with valid data. The system would then write
the burst mode configuration register command se-
tions” for further details.
Once the system has written the “Set Burst Mode Con-
figuration Register” command sequence, the device is
enabled for synchronous reads only.
The initial word is output t
IACC after the active edge of
the first CLK cycle. Subsequent words are output t
BACC
after the active edge of each successive clock cycle,
which automatically increments the internal address
counter. Note that the device has a fixed internal ad-
dress boundary that occurs every 64 words, starting at
address 00003Fh. During the time the device is out-
putting data at this fixed internal address boundary
(address 00003Fh, 00007Fh, 0000BFh, etc.), a two
cycle latency occurs before data appears for the next
address (address 000040h, 000080h, 0000C0h, etc.).
The RDY output indicates this condition to the system
by pulsing low. For non-handshaking devices, there is
no two cycle latency between 3Fh and 40h (or multiple
thereof). See Table 10.
For handshaking devices, if the address latched is
3Dh (or 64 multiple), an additional cycle latency oc-
curs prior to the initial access. If the address latched is
3Eh (or 64 multiple) two additional cycle latency oc-
curs prior to the initial access and the 2 cycle latency
between 3Fh and 40h (or 64 multiple) will not occur.
For 3Fh latched addresses (or 64 multiple) three addi-
tional cycle latency occurs prior to the initial access
and the 2 cycle latency between 3Fh and 40h (or 64
multiple) will not occur.
The device will continue to output sequential burst
data, wrapping around to address 000000h after it
reaches the highest addressable memory location,
until the system drives CE# high, RESET# low, or
AVD# low in conjunction with a new address. See
If the host system crosses the bank boundary while
reading in burst mode, and the device is not program-
ming or erasing, a two-cycle latency will occur as de-
scribed above in the subsequent bank. If the host
system crosses the bank boundary while the device is
programming or erasing, the device will provide read
status information. The clock will be ignored. After the
host has completed status reads, or the device has
completed the program or erase operation, the host
can restart a burst operation using a new address and
AVD# pulse.
If the clock frequency is less than 6 MHz during a burst
mode operation, additional latencies will occur. RDY
indicates the length of the latency by pulsing low.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three modes are of the linear wrap
around design, in which a fixed number of words are
read from consecutive addresses. In each of these
modes, the burst addresses read are determined by
the group within which the starting address falls. The
groups are sized according to the number of words
read in a single burst sequence for a given mode (see
Table 2.
Burst Address Groups
As an example: if the starting address in the 8-word
mode is 39h, the address range to be read would be
38-3F h, and t he b u rs t s equenc e would be
39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence
begins with the starting address written to the device,
Mode
Group Size Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h, ...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh, ...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh, ...
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