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參數(shù)資料
| 型號(hào)： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁(yè)數(shù)： | 47/71頁(yè) |
| 文件大小： | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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51
Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the
first of either the rising edge of AVD# or the active edge of CLK.
3. See the “Flash Erase And Programming Performance” section for more information.
4. Does not include the preprogramming time.
Parameter
Description
All Speed
Options
Unit
JEDEC
Standard
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
ns
t
AVWL
t
AS
Address Setup Time
Synchronous
Min
5
ns
Asynchronous
0
t
WLAX
t
AH
Address Hold Time
Synchronous
Min
7
ns
Asynchronous
45
t
ACS
Address Setup Time to CLK (Note 2)
Min
5
ns
t
ACH
Address Hold Time to CLK (Note 2)
Min
7
ns
t
DVWH
t
DS
Data Setup Time
Min
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
Min
0
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
50
ns
t
WHWL
t
WPH
Write Pulse Width High
Min
30
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 3)
Typ
8
s
t
WHWH1
t
WHWH1
Accelerated Programming Operation (Note 3)
Typ
2.5
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Notes 3, 4)
Typ
0.2
sec
Chip Erase Operation (Notes 3, 4)
26.8
t
VID
V
Rise and Fall Time
Min
500
ns
t
VIDS
V
ACC Setup Time (During Accelerated Programming)
Min
1
s
t
VCS
V
CC Setup Time
Min
50
s
t
CSW1
Clock Setup Time to WE# (Asynchronous)
Min
5
ns
t
CSW2
Clock Setup Time to WE# (Synchronous)
Min
1
ns
t
CHW
Clock Hold Time from WE#
Min
1
ns
t
ELWL
t
CS
CE# Setup Time to WE#
Min
0
ns
t
AVSW
AVD# Setup Time to WE#
Min
5
ns
t
AVHW
AVD# Hold Time to WE#
Min
5
ns
t
AVHC
AVD# Hold Time to CLK
Min
5
ns
t
AVDP
AVD# Low Time
Min
12
ns
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