參數(shù)資料
型號(hào)： AM54BDS128AGT89IT
廠商： ADVANCED MICRO DEVICES INC
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 10 X 10 MM, 0.80 PITCH, FBGA-93
文件頁(yè)數(shù)： 20/71頁(yè)
文件大?。?/td> 1031K
代理商： AM54BDS128AGT89IT
27
Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
Configuration Register
Table 12 shows the address bits that determine the
configuration register settings for various device func-
tions.
Table 12.
Burst Mode Configuration Register
Note:Device will be in the default state upon power-up or hardware reset.
Sector Lock/Unlock Command Sequence
The sector lock/unlock command sequence allows the
system to determine which sectors are protected from
accidental writes. When the device is first powered up,
all sectors are locked. To unlock a sector, the system
must write the sector lock/unlock command sequence.
Two cycles are first written: addresses are don’t care
and data is 60h. During the third cycle, the sector ad-
dress (SLA) and unlock command (60h) is written,
while specifying with address A6 whether that sector
should be locked (A6 = V
IL) or unlocked (A6 = VIH).
After the third cycle, the system can continue to lock or
unlock additional cycles, or exit the sequence by writ-
ing F0h (reset command).
Note that the last two outermost boot sectors can be
locked by taking the WP# signal to V
IL.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins (prior to the third cycle). This
resets the bank to which the system was writing to the
read mode. If the program command sequence is writ-
ten to a bank that is in the Erase Suspend mode, writ-
ing the reset command returns that bank to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Sus-
pend mode, writing the reset command returns that
bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
The reset command is used to exit the sector lock/un-
lock sequence.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
the address and data requirements. The autoselect
command sequence may be written to an address
Address BIt
Function
Settings (Binary)
A19
Set Device Read Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
A18
RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
A17
Clock
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
A16
Burst Read Mode
00 = Continuous (default)
01 = 8-word linear with wrap around
10 = 16-word linear with wrap around
11 = 32-word linear with wrap around
A15
A14
Programmable
Wait State
000 = Data is valid on the 2nd active CLK edge after AVD# transition to V
IH
001 = Data is valid on the 3rd active CLK edge after AVD# transition to V
IH
010 = Data is valid on the 4th active CLK edge after AVD# transition to V
IH
011 = Data is valid on the 5th active CLK edge after AVD# transition to V
IH
100 = Data is valid on the 6th active CLK edge after AVD# transition to V
IH
101 = Data is valid on the 7th active CLK edge after AVD# transition to V
IH (default)
A13
A12
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