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參數(shù)資料
| 型號(hào)： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁數(shù)： | 21/71頁 |
| 文件大小： | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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July 23, 2002
Am54BDS128AG
28
ADV ANCE
I N FO RMAT I O N
within a bank that is either in the read or erase-sus-
pend-read mode. The autoselect command may not
be written while the device is actively programming or
erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
toselect command. The bank then enters the autose-
lect mode. No subsequent data will be made available
if the autoselect data is read in synchronous mode.
The system may read at any address within the same
bank any number of times without initiating another
autoselect command sequence. The following table
describes the address requirements for the various
autoselect functions, and the resulting data. BA repre-
sents the bank address, and SA represents the sector
address. The device ID is read in three cycles.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 13 shows the address
and data requirements for the program command se-
quence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
min e t h e s t at u s of t h e pr og ra m op er at i o n b y
monitoring DQ7 or DQ6/DQ2. Refer to the “Flash
Write Operation Status” section on page 32 section for
information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from
“0” back to a “1.” Attempting to do so may cause that
bank to set DQ5 = 1, or cause the DQ7 and DQ6 sta-
tus bit to indicate the operation was successful. How-
ever, a succeeding read will show that the data is still
“0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to prima-
rily program to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip
erase and sector erase sequences in the unlock by-
pass mode. The erase command sequences are four
cycles in length instead of six cycles. Table 13, “Com-
mand Definitions,” on page 31 shows the require-
ments for the unlock bypass command sequences.
During the unlock bypass mode, only the Unlock By-
pass Program, Unlock Bypass Sector Erase, Unlock
Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the
system must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
The device offers accelerated program operations
through the ACC input. When the system asserts V
ID
on this input, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC input to accelerate the operation.
Figure 2 illustrates the algorithm for the program oper-
ation. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
ings,” on page 52 for timing diagrams.
Description
Address
Read Data
Description
Address
Read Data
Manufacturer ID
(BA) + 00h
0001h
Device ID, Word 1
(BA) + 01h
227Eh
Device ID, Word 2,
Top Boot
(BA) + 0Eh
2204h (1.8 V V
IO)
Device ID, Word 2,
Bottom Boot
(BA) + 0Eh
2224h (1.8 V V
IO)
Device ID, Word 3
(BA) + 0Fh
2201h
Sector Block
Lock/Unlock
(SA) + 02h
0001 (locked),
0000 (unlocked)
Handshaking
(BA) + 03h
43h (provided),
42h (not provided)
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