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參數(shù)資料
| 型號： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁數(shù)： | 27/71頁 |
| 文件大?。?/td> | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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33
Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
RDY: Ready
The RDY is a dedicated output that, by default, indi-
cates (when at logic low) the system should wait 1
clock cycle before expecting the next word of data.
Using the RDY Configuration Command Sequence,
RDY can be set so that a logic low indicates the sys-
tem should wait 2 clock cycles before expecting valid
data.
RDY functions only while reading data in burst mode.
The following conditions cause the RDY output to be
low: during the initial access (in burst mode), and after
the boundary that occurs every 64 words beginning
with the 64th address, 3Fh.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress in the same bank, and is valid after the rising
edge of the final WE# pulse in the command sequence
(prior to the program or erase operation), and during
the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. When the operation is complete, DQ6
stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 s, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
The system can use DQ6 and DQ2 together to deter-
mine wh ether a sector is a ctively erasing o r is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 ms after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
See the following for additional information: Figure 4
(toggle bit flowchart), DQ6: Toggle Bit I (description),
(During Embedded Algorithm),” on page 58 (toggle bit
timing diagram), and Table 14, “DQ6 and DQ2 Indica-
Figure 5.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
START
No
Yes
DQ5 = 1?
No
Yes
DQ6 = Toggle?
No
Read Byte
(DQ7–DQ0)
Address = VA
DQ6 = Toggle?
Read Byte Twice
(DQ7–DQ0)
Adrdess = VA
Read Byte
(DQ7–DQ0)
Address = VA
FAIL
PASS
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
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