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參數(shù)資料
| 型號： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁數(shù)： | 55/71頁 |
| 文件大?。?/td> | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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59
Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
AC CHARACTERISTICS
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm operation
is complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Burst Mode
Configuration Register). When A18 = 1 in the Burst Mode
Configuration Register, RDY is active one clock cycle
before data.
4. AVD# must toggle between data reads.
5. CE#f refers to active flash die.
Figure 29.
Synchronous Data Polling Timings/Toggle Bit Timings
AC CHARACTERISTICS)
Notes:
1. RDY active with data (A18 = 0 in the Burst Mode Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Burst Mode Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not
crossing a bank in the process of performing an erase or program.
Figure 30.
Latency with Boundary Crossing
CE#f
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data
VA
tIACC
CLK
Address (hex)
C60
C61
C62
C63
C64
C65
C66
C67
D60
D61
D62
D63
D64
D65
D66
D67
(stays high)
AVD#
RDY
Data
Address boundary occurs every 64 words, beginning at address
00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing.
3C
3D
3E
3F
40
41
42
43
latency
RDY
latency
tRACC
(Note 1)
(Note 2)
tRACC
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