參數(shù)資料
型號(hào)： AM54BDS128AGT89IT
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 10 X 10 MM, 0.80 PITCH, FBGA-93
文件頁(yè)數(shù)： 22/71頁(yè)
文件大小： 1031K
代理商： AM54BDS128AGT89IT
29
Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
Figure 2.
Erase Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 13,
dress and data requirements for the chip erase com-
mand sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7 or DQ6/DQ2.
page 32 section for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
The host system may also initiate the chip erase com-
mand sequence while the device is in the unlock by-
pass mode. The command sequence is two cycles
cycles in length instead of six cycles. See Table 13 for
details on the unlock bypass command sequences.
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters and tim-
ing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 13 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of no less than 35 s occurs. During the
time-out period, additional sector addresses and sec-
tor erase commands may be written. Loading the sec-
tor erase buffer may be done in any sequence, and
the number of sectors may be from one sector to all
sectors. The time between these additional cycles
must be less than 50 s, otherwise erasure may begin.
Any sector erase address and command following the
exceeded time-out may or may not be accepted. It is
recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the time-out
period resets that bank to the read mode. The system
must rewrite the command sequence and any addi-
tional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See “DQ3: Sector Erase
Timer” section on page 34.). The time-out begins from
the rising edge of the final WE# pulse in the command
sequence.
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 13 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
相關(guān)PDF資料
PDF描述
AM7200-65RC 256 X 9 OTHER FIFO, 65 ns, PDIP28
AM7200-80RC 256 X 9 OTHER FIFO, 80 ns, PDIP28
AM7201-25DC 512 X 9 OTHER FIFO, 25 ns, CDIP28
AM7203-65JC 2K X 9 OTHER FIFO, 65 ns, PQCC32
AM7831X DUAL LINE DRIVER, UUC16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM54S 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Four-Bit Shifter With Three-State Outputs
AM54S350 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Four-Bit Shifter With Three-State Outputs
AM-55 制造商:Amprobe Test Tools 功能描述:Digital Multimeter
AM-550 功能描述:數(shù)字萬(wàn)用表 Digital Multimeter TRMS RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類(lèi)型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持:
AM55-0001 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:140 mW Power Amplifier with T/R and Diversity Switches 2.42.5 GHz
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*