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參數(shù)資料
| 型號： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁數(shù)： | 17/71頁 |
| 文件大?。?/td> | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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July 23, 2002
Am54BDS128AG
24
ADV ANCE
I N FO RMAT I O N
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
“Reset Command” section on page 27 section for
more information.
nous (Burst) Read Operation” sections for more
information. The Asynchronous Read and Synchro-
nous/Burst Read tables provide the read parameters,
Set Burst Mode Configuration Register
Command Sequence
The device uses a burst mode configuration register to
set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY con-
figuration, and synchronous mode active. The burst
mode configuration register must be set before the de-
vice will enter burst mode.
The burst mode configuration register is loaded with a
three-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the
data should be C0h, address bits A11–A0 should be
555h, and address bits A19–A12 set the code to be
latched. The device will power up or after a hardware
reset with the default setting, which is in asynchronous
mode. The register must be set before the device can
enter synchronous mode. The burst mode configura-
tion register can not be changed during device opera-
tions (program, erase, or sector lock).
Figure 1.
Synchronous/Asynchronous State
Diagram
Read Mode Setting
On power-up or hardware reset, the device is set to be
in asynchronous read mode. This setting allows the
system to enable or disable burst mode during system
operations. Address A19 determines this setting: “1’
for asynchronous mode, “0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the de-
vice of the number of clock cycles that must elapse
after AVD# is driven active before data will be avail-
able. This value is determined by the input frequency
of the device. Address bits A14–A12 determine the
setting (see Table 8).
The wait state command sequence instructs the de-
vice to set a particular number of clock cycles for the
initial access in burst mode. The number of wait states
that should be programmed into the device is directly
related to the clock frequency.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(A19 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(A19 = 1)
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