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| 型號： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁數(shù)： | 5/71頁 |
| 文件大小： | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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13
Am54BDS128AG
July 23, 2002
ADV ANCE
I N FO RMAT I O N
Table 1.
Device Bus Operations
Legend: L = Logic Low = V
IL, H = Logic High = VIH, VID = 9–11 V, VHH
= 9.0 ± 0.5 V, X = Don’t Care, A
IN = Address In, DIN = Data In, DOUT
=Data Out
= Rising edge of Pulse Low
= Active edge of CLK,
= Pulse Low,
Notes:
1.
Other operations except for those indicated in this column are
inhibited.
2.
Do not apply CE#f = V
IL, CE1#s = VIL and CE2s = VIH at the same
time.
3.
Either CE1#s = V
IH or CE2s = VIL will disable the SRAM. If one of
these conditions is true, the other CE input is don’t care.
4.
X = Don’t care or open LB#s or UB#s.
5.
Default edge of CLK is the rising edge.
6.
The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector
Lock/Unlock Command Sequence”section.
7.
If ACC = V
HH, all sectors will be protected.
8.
If WP# = V
IL, sectors 0,1 (bottom boot) or sectors 132, 133 (top
boot) are protected. If WP# = V
IH, the protection applied to the
aforementioned sectors depends on whether they were last
protected or unprotected using the method described in “Sector
Lock/Unlock Command Sequence”. Note that WP# must not be
left floating or unconnected.
9.
Active flash is device being addressed.
Operation
CE#f
Active
CE#f
Inactive
CE1#
s
CE2s
OE# WE#
A
[21–0]
DQ
[15–8]
DQ
[7–0]
LB#s UB#s
RESET# CLK
AVD#
Asynchronous Read from
Flash,
Addresses Latched
LH
H
L
H
AIN
I/O
X
H
X
Asynchronous Read from
Flash,
Addresses Steady State
LH
H
L
H
A
IN
I/O
X
H
X
L
Asynchronous Write to Flash
L
H
L
H
L
A
IN
I/O
X
H
X
L
Synchronous Write to Flash
L
H
L
H
L
A
IN
I/O
X
H
X
CE# Standby
H
L
X
Hi-Z
X
H
X
Output Disable
L
H
HL
H
Hi-Z
LX
HX
X
HL
X
L
Hardware Reset
X
H
L
X
Hi-Z
X
L
X
Read from SRAM
H
L
H
L
H
AIN
DOUT
LL
HX
X
DOUT
Hi-Z
H
L
Hi-Z
D
OUT
LH
Write to SRAM
H
L
H
X
L
A
IN
D
IN
D
IN
LL
HX
X
D
IN
Hi-Z
H
L
HI-Z
D
IN
LH
Flash Burst Read Operations
Load Starting Burst Address
L
H
L
X
H
Addr In
X
H
Advance Burst to next
address with appropriate
Data presented on the Data
Bus
LH
H
L
H
HIGH
Z
Burst
Data Out
XX
H
Terminate current Burst read
cycle
H
L
X
H
Hi-Z
X
H
X
Terminate current Burst read
cycle via RESET#
X
H
L
X
H
Hi-Z
X
L
X
Terminate current Burst read
cycle and start new Burst
read cycle
L
H
L
X
H
Hi-Z
I/O
X
H
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