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參數(shù)資料
| 型號： | AM54BDS128AGT89IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件頁數(shù)： | 19/71頁 |
| 文件大小： | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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July 23, 2002
Am54BDS128AG
26
ADV ANCE
I N FO RMAT I O N
modes operate in a fashion similar to the eight-word
mode.
Table 11 shows the address bits and settings for the
four burst read modes.
Table 11.
Burst Read Mode Settings
Note: Upon power-up or hardware reset the default setting
is continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising
edge of the clock after the initial synchronous access
time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be
set so that the falling clock edge is active for all syn-
chronous accesses. Address bit A17 determines this
setting; “1” for rising active, “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will
output V
OH whenever there is valid data on the out-
puts. The device can be set so that RDY goes active
one data cycle before active data. Address bit A18 de-
termines this setting; “1” for RDY active with data, “0”
for RDY active one clock cycle before valid data.
Burst Modes
Address Bits
A16
A15
Continuous
0
8-word linear wrap around
0
1
16-word linear wrap around
1
0
32-word linear wrap around
1
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