參數(shù)資料
型號: H5MS5162DFR-K3M
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁數(shù): 50/62頁
文件大小: 1314K
代理商: H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
54
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
Status Register Read
The Status Register contains the specific die information such as density, device type, data bus width, refresh rate,
revision ID and manufacturers. The Status Register is only for READ. Below figure is Status Register Read Timing Dia-
gram.
To read out the Status Register values, BA[1:0] set to 01b and A[12:0] set to all 0 with MRS command followed by
Read command with that BA[1:0] are Don’t care and A[12:0] set to all 0.
Note)
1. SRR can only be issued after power-up sequence is complete.
2. SRR can only be issued with all banks precharged.
3. SRR CL is unchanged from value in the mode register.
4. SRR BL is fixed at 2.
5. tSRR = 2 CLK (min)
6. tSRC = CL + 1. (min time between READ to next valid command)
7. No commands other than NOP and DESELECT are allowed between the SRR and the READ.
CMD
tCK
tRP
tSRR
NOP
MRS
NOP
READ
NOP
CMD
Register
Value Out
tSRC
CLK
CMD
BA[1:0]
Add
DQS
DQ[15:0]
01
0
CL = 3
Don
’’’’t care
PRE All or PRE
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