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APPENDIX C V
R
4120A COPROCESSOR 0 HAZARDS
666
Preliminary User’s Manual S14767EJ1V0UM00
Table C-1. V
R
4120A CPU Coprocessor 0 Hazards
Operation
Source
Destination
Source Name
No. of
Cycles
Destination Name
No. of
Cycles
MTC0
cpr rd
5
MFC0
cpr rd
3
TLBR
Index, TLB
2
PageMask, EntryHi, EntryLo0,
EntryLo1
5
TLBWI
TLBWR
Index or Random, PageMask,
EntryHi, EntryLo0, EntryLo1
2
TLB
5
TLBP
PageMask, EntryHi
2
Index
6
ERET
EPC or ErrorEPC, TLB
2
Status.EXL, Status.ERL
4
Status
2
CACHE Index Load Tag
TagLo, TagHi, PErr
5
CACHE Index Store Tag
TagLo, TagHi, PErr
3
CACHE Hit ops.
cache line
3
cache line
5
Coprocessor usable test
Status.CU, Status.KSU,
Status.EXL, Status.ERL
2
Instruction fetch
EntryHi.ASID, Status.KSU,
Status.EXL, Status.ERL,
Status.RE, Config.K0C
2
TLB
2
Instruction fetch
EPC, Status
4
exception
Cause, BadVAddr, Context,
XContext
5
Interrupt signals
Cause.IP, Status.IM, Status.IE,
Status.EXL, Status.ERL
2
Load/Store
EntryHi.ASID, Status.KSU,
Status.EXL, Status.ERL,
Status.RE, Config.K0C, TLB
3
Config.AD, Config.EP
3
WatchHi, WatchLo
3
Load/Store exception
EPC, Status, Cause, BadVAddr,
Context, XContext
5
TLB shutdown
Status.TS
2 (Inst.),
4 (Data)
Cautions 1. If the setting of the K0 bit in the Config register is changed to uncached mode by MTC0, the
accessed memory area is switched to the uncached one at the instruction fetch of the third
instruction after MTC0.
2. A stall of several instructions occurs if a jump or branch instruction is executed
immediately after the setting of the ITS bit in the Status register.