![](http://datasheet.mmic.net.cn/380000/-PD98501_datasheet_16745028/-PD98501_253.png)
CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S14767EJ1V0UM00
253
3.4.7 SDRAM
3.4.7.1 SDRAM address range
System Memory can be populated with SDRAM chips, and it must have an access time of 10ns or less. The
System Controller supports 16Mbit or 64Mbit and 128Mbit SDRAM at locations 0000_0000H through 01FF_FFFFH in
the physical memory space on V
R
4120A. The SDRAM supports CPU cache operations,.
Table 3-8. SDRAM Size Configuration at Reset
SDMDR.SDS
SDRAM Size
Address Range
00
4MB
0000_0000H through 003F_FFFH
01
8MB
0000_0000H through 007F_FFFH
10
16MB
0000_0000H through 00FF_FFFH
11
32MB
0000_0000H through 01FF_FFFH
3.4.7.2 SDRAM device configurations
The controller supports the following 16Mbit 64Mbit and 128Mbit. NEC SDRAM parts and configurations in System
Memory. Following Table shows some of the SDRAM configurations supported for system memory.
Table 3-9. SDRAM Configurations Supported
Memory
Size
SMA Address Bits
Required
Organization
(bank x word x bit)
Quantity
NEC Part Number
4MB
12:0
2 x 0.5M x 16
2
μ
PD4516161
8MB
12:0
4 x 0.5M x 32
1
μ
PD4564323
16MB
13:0
4 x 1.0M x 16
2
μ
PD4564163
32MB
13:0
4 x 2.0M x 16
2
μ
PD45128163
3.4.7.3 SDRAM burst-type and banks
The terms interleaved and bank have multiple meanings in the context of memory design using SDRAM chips. The
meanings are:
Banks (applied to memory modules and SDRAM chips in different ways): The banks referenced with respect to
memory modules differ from the banks inside an SDRAM chip. For module, This controller does not support
what identifies their bank. Following Table shows bank select signals.
Table 3-10. SDRAM Bank Select Signals Mapping
MuxAd Bank Signal
Memory Bank select inputs
NEC Parts Number
SMA [11]
A[11]
μ
PD4516161
SMA [12:11]
BA[1:0]
μ
PD4564323
SMA [13:12]
A[13:12]
μ
PD4564163
SMA [13:12]
A[13:12]
μ
PD45128163