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CHAPTER 6 USB CONTROLLER
392
Preliminary User’s Manual S14767EJ1V0UM00
6.2.2.16
USB Tx EndPoint Status Register (U_TEPSR): 48H
31
16
15
0
7
8
15
16
EP5TS
17
18
Reserved
EP1TS
Reserved
9
10
EP3TS
Reserved
17
18
EP0TS
Reserved
1
2
Register that indicates the status of the EndPoint being used for data sending.
Bit
Field
Description
R/W
31-26
Reserved
Reserved for future use
R
25-24
EP5TS
(EP5 Tx Status)
Register that indicates the send status of EndPoint5
This register is not cleared, even if read.
00: There is no data scheduled to be sent (Idle)
01: There is one data item scheduled to be sent
10: There are two data items that are scheduled
to be sent (Busy)
R
23-18
Reserved
Reserved for future use
R
17-16
EP3TS
(EP3 Tx Status)
Register that indicates the send status of EndPoint3
This register is not cleared, even if read.
00: There is no data scheduled to be sent (Idle)
01: There is one data item scheduled to be sent
10: There are two data items that are scheduled
to be sent (Busy)
R
15-10
Reserved
Reserved for future use
R
9-8
EP1TS
(EP1 Tx Status)
Register that indicates the send status of EndPoint1
This register is not cleared, even if read.
00: There is no data scheduled to be sent (Idle)
01: There is one data item scheduled to be sent
10: There are two data items that are scheduled
to be sent (Busy)
R
7-2
Reserved
Reserved for future use
R
1-0
EP0TS
(EP1 Tx Status)
Register that indicates the send status of EndPoint0
This register is not cleared, even if read.
00: There is no data scheduled to be sent (Idle)
01: There is one data item scheduled to be sent
10: There are two data items that are scheduled
to be sent (Busy)
R