![](http://datasheet.mmic.net.cn/380000/-PD98501_datasheet_16745028/-PD98501_24.png)
24
Preliminary User’s Manual S14767EJ1V0UM00
LIST OF TABLES (3/3)
Table No.
Title
Page
5-4 DMA and FIFO Management Registers Map.......................................................................................................345
5-5 Interrupt and Configuration Registers Map .........................................................................................................345
5-6 Attribute for Transmit Descriptor.........................................................................................................................366
5-7 Attribute for Receive Descriptor..........................................................................................................................367
7-1 Correspondence between Baud Rates and Divisors...........................................................................................448
9-1 EEPROM Initial Data ..........................................................................................................................................462
9-2 EEPROM Command List ....................................................................................................................................462
A-1 CPU Instruction Operation Notations..................................................................................................................466
A-2 Load and Store Common Functions...................................................................................................................467
A-3 Access Type Specifications for Loads/Stores.....................................................................................................468
C-1 V
R
4120A CPU Coprocessor 0 Hazards..............................................................................................................666
C-2 Calculation Example of CP0 Hazard and Number of Instructions Inserted ........................................................669