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Preliminary User’s Manual S14767EJ1V0UM00
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4.8
Operations................................................................................................................................ 311
4.8.1 Work RAM usage.............................................................................................................................311
4.8.2 Transmission function......................................................................................................................313
4.8.3 Receiving function............................................................................................................................325
4.8.4 Mailbox.............................................................................................................................................331
4.8.5 ABR function....................................................................................................................................332
CHAPTER 5 ETHERNET CONTROLLER........................................................................................... 339
5.1
Overview................................................................................................................................... 339
5.1.1 Features...........................................................................................................................................339
5.1.2 Block diagram of Ethernet controller block.......................................................................................339
5.2
Register .................................................................................................................................... 341
5.2.1 Statistics counter registers...............................................................................................................343
5.2.2 DMA and FIFO management registers ............................................................................................345
5.2.3 Interrupt and configuration registers ................................................................................................345
5.2.4 Detail of MAC control registers ........................................................................................................346
5.2.5 Detail of DMA and FIFO management registers..............................................................................357
5.2.6 Detail of interrupt and configuration registers...................................................................................363
5.3
Operation.................................................................................................................................. 365
5.3.1 Initialization......................................................................................................................................365
5.3.2 Buffer structure for Ethernet block ...................................................................................................365
5.3.3 Buffer descriptor format....................................................................................................................366
5.3.4 Frame transmission .........................................................................................................................367
5.3.5 Frame reception...............................................................................................................................370
CHAPTER 6 USB CONTROLLER....................................................................................................... 373
6.1
Overview................................................................................................................................... 373
6.1.1 Features...........................................................................................................................................373
6.1.2 Internal block diagram......................................................................................................................374
6.2
Register Set.............................................................................................................................. 375
6.2.1 Register map....................................................................................................................................375
6.2.2 Explanation of registers....................................................................................................................377
6.3
USB Attachment Sequence.................................................................................................... 409
6.4
Initialization.............................................................................................................................. 410
6.4.1 Receive pool setting.........................................................................................................................411
6.4.2 Send/receive mailbox setting...........................................................................................................411
6.5
Data Send Function................................................................................................................. 413
6.5.1 Overview of send processing...........................................................................................................413
6.5.2 Send buffer configuration.................................................................................................................413
6.5.3 Data send modes.............................................................................................................................416
6.5.4 V
R
4120A RISC processor processing at data sending.....................................................................417
6.5.5 USB controller processing at data sending......................................................................................420
6.5.6 Tx indication.....................................................................................................................................422
6.6
Data Receive Function............................................................................................................ 423
6.6.1 Overview of receive processing.......................................................................................................423
6.6.2 Receive buffer configuration ............................................................................................................424
6.6.3 Receive pool settings.......................................................................................................................426
6.6.4 Data receive mode...........................................................................................................................427