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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	119/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

Preliminary User’s Manual S14767EJ1V0UM00

2.4.4 Pipeline operation

The operation of the pipeline is illustrated by the following examples that describe how typical instructions are

executed. The instructions described are six: ADD, JALR, BEQ, TLT, LW, and SW. Each instruction is taken through

the pipeline and the operations that occur in each relevant stage are described.

2.4.4.1 Add instruction (ADD rd, rs, rt)

1 of the IF stage, the eleven least-significant bits of the virtual access are used to access

the instruction cache. In

2 of the IF stage, the cache index is compared with the page frame

number and the cache data is read out. The virtual PC is incremented by 4 so that the next

instruction can be fetched.

The MIPS16 instruction is translated into a 32-bit length instruction (during MIPS16 instruction

2, the 2-port register file is addressed with the rs and rt fields and the register data is

valid at the register file output. At the same time, bypass multiplexers select inputs from either

the EX- or DC-stage output in addition to the register file output, depending on the need for an

operand bypass.

The ALU controls are set to do an A + B operation. The operands flow into the ALU inputs, and

the ALU operation is started. The result of the ALU operation is latched into the ALU output

latch during

This stage is a NOP for this instruction. The data from the output of the EX stage (the ALU) is

moved into the output latch of the DC.

1, the WB latch feeds the data to the inputs of the register file, which is addressed by

the rd field. The file write strobe is enabled. By the end of

1, the data is written into the file.

Figure 2-18. ADD Instruction Pipeline Activities (In MIPS III Instruction Mode)

Figure 2-19. ADD Instruction Pipeline Activities (In MIPS16 Instruction Mode)

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