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型號(hào)：	μPD98501
廠(chǎng)商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	254/671頁(yè)
文件大小：	2229K
代理商：	ΜPD98501

CHAPTER 3 SYSTEM CONTROLLER

Preliminary User’s Manual S14767EJ1V0UM00

Burst Type (applies to SDRAM chips): The burst type of a single SDRAM chip is programmed in the chip’s

Mode Register to be either interleaved or sequential. This concept relates only to the word-order in which data

is read into and written out of the SDRAM chip. The concept does not relate to the number of words transferred

in a given clock cycle. The burst type for all SDRAM chips attached to the

PD98501 is configured during the

Memory Initialization procedure. The memory controller in the System Controller does NOT support the

interleaved burst mode and support only sequential burst mode.

3.4.7.4 SDRAM word ordering

Following Table shows the word-address order for a 4-word instruction-cache line fill from SDRAM. This order is

determined by the SDRAM chips’ burst type, which is programmed during the Memory Initialization procedure. The

memory controller programs the burst type and word order the same for all SDRAM chips connected to it (in the

System Memory ranges). The term “sequential” in this table refers to the SDRAM burst type. Burst length depends

only on the access type performed by the CPU.

Table 3-11. SDRAM Word Order for Instruction-Cache Line-Fill

SDRAM-Chip Burst Type

Start Column Address A1.A0

not supported

not supported

not supported

not supported

The memory controller does not support the interleaved burst type for SDRAMs. It assumes that all

SDRAMs are initialized to the sequential burst type, using a burst length of 4 words.

3.4.7.5 SDRAM signal connections

Following Figure shows how the NEC 16Mbit SDRAMs are connected for System Memory. SMA[11] is the bank

select signal. In command cycle, SMA[11] low selects Bank A and SMA[11] High selects Bank B. Both banks share

the same SDCSB, SDRASB, SDCASB, and SDWEB signals.

The two banks of System Memory behave as two halves of the address range, with the highest unmasked address

bit controlling bank selection.

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