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CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S14767EJ1V0UM00
225
3.2 Registers
3.2.1 Register summary
Following Table summarizes the controller’s register set. The base address for the set is 1000_0000H in the
physical address space.
Offset
Name
R/W
Access
Description
Default
00H
04H
08H
0CH
10H
14H
18H
1CH
20H:
2FH
30H
34H
38H
3CH
40H:
4BH
4CH
50H
54H:
7FH
80H
80H
80H
84H
84H
88H
88H
8CH
90H
94H
98H
9CH
A0H
A4H
A8H
ACH
B0H
B4H
B8H
BCH
C0H
C4H:
CFH
S_GMR
S_GSR
S_ISR
S_IMR
S_NSR
S_NMR
S_VER
S_IOR
N/A
R/W
R
RC
R/W
RC
R/W
R
R/W
----
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
----
General Mode Register
General Status Register
Interrupt Status Register
Interrupt Mask Register
NMI Status Register
NMI Mask Register
Version Register
IO Port Register
Reserved
00000000H
unknown
00000000H
00000000H
00000000H
00000000H
00000100H
00000000H
unknown
S_WRCR
S_WRSR
S_PWCR
S_PWSR
N/A
W
R
R/W
R
----
W/H/B
W/H/B
W/H/B
W/H/B
----
Warm Reset Control Register
Warm Reset Status Register
Power Control Register
Power Control Status Register
Reserved
00000000H
00000000H
00000000H
00000000H
unknown
ITCNTR
ITSETR
N/A
R/W
R/W
----
W/H/B
W/H/B
----
IBUS Timeout Timer Control Register
IBUS Timeout Timer Set Register
Reserved
00000000H
80000000H
unknown
UARTRBR
UARTTHR
UARTDLL
UARTIER
UARTDLM
UARTIIR
UARTFCR
UARTLCR
UARTMCR
UARTLSR
UARTMSR
UARTSCR
DSUCNTR
DSUSETR
DSUCLRR
DSUTIMR
TMMR
TM0CSR
TM1CSR
TM0CCR
TM1CCR
N/A
R
W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R/W
R/W
R/W
R
R
----
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
----
UART, Receiver Buffer Register [DLAB=0,READ]
UART, Transmitter Holding Register [DLAB=0,WRITE]
UART, Divisor Latch LSB Register [DLAB=1]
UART, Interrupt Enable Register [DLAB=0]
UART, Divisor Latch MSB Register [DLAB=1]
UART, Interrupt ID Register [READ]
UART, FIFO control Register [WRITE]
UART, Line control Register
UART, Modem Control Register
UART, Line status Register
UART, Modem Status Register
UART, Scratch Register
DSU Control Register
DSU Dead Time Set Register
DSU Clear Register
DSU Elapsed Time Register
Timer Mode Register
Timer CH0 Count Set Register
Timer CH1 Count Set Register
Timer CH0 Current Count Register
Timer CH1 Current Count Register
Reserved
unknown
unknown
unknown
unknown
unknown
unknown
unknown
unknown
unknown
unknown
unknown
unknown
00000000H
80000000H
00000000H
00000000H
00000000H
00000000H
00000000H
FFFFFFFFH
FFFFFFFFH
unknown