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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	276/671頁(yè)
文件大小：	2229K
代理商：	ΜPD98501

CHAPTER 4 ATM CELL PROCESSOR

Preliminary User’s Manual S14767EJ1V0UM00

4120A and RISC Core share external memory spaces. Shared memory will be implemented by using SDRAM

devices. The address in V

4120A RISC Processor memory space will be determined by S/W and notified to RISC

Core by setting A_IBBAR (IBus data Base Address Register). Its capacity depends on the total capacity of physical

memory, but not exceeds 4MB.

4.2.1 Work RAM and register space

Work RAM and Register Space is shown in Figure 4-7. It contains Work RAM, PHY space, and register space.

The capacity of Work RAM is 16KB max. It can be accessed by using “Indirect command”. In register space, A_GMR

(general mode register), A_GSR (general status register), A_CMR (command register), A_CER (command extension

management I/F.

Figure 4-7. Work RAM and Register Space

ATM Cell Processor

Reserved for

Internal memory space and peripheral space are exclusively used by RISC Core and cannot be seen by other

blocks. Internal memory space will be used as stack and global variable space. In peripheral space, an interrupt

controller and some other special blocks will be mapped. Scheduling table, VC lookup table, IP lookup table, Cell

Timer, and ABR rate translator will be mapped in peripheral space as well.

Instruction memory space will be placed in SDRAM space. The address V

4120A RISC Processor memory space

will be determined by S/W and notified to RISC Core by setting A_INBAR (Instruction Base Address Register).

Instruction memory space is mapped on SDRAM space to achieve faster instruction access.

4.2.2 Shard memory

ATM Cell Processor has at most 4MB of buffer memory that is mainly used as cell buffer and packet buffer. This

memory will be implemented off the chip, or on SDRAM. V

4120A RISC Processor can access this memory via.

System Controller. Address of External Shared Memory will be translated into V

4120A RISC Processor memory

space by adding content of A_IBBAR (IBus data Base Address Register). A_IBBAR will be set during initializing

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