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CHAPTER 2 V
R
4120A
Preliminary User’s Manual S14767EJ1V0UM00
185
When the MIPS16 instruction is disabled, the EPC register contains the address of the instruction that caused the
exception. However, if this instruction is in a branch delay slot, the EPC register contains the address of the
preceding jump or branch instruction, and the BD bit of the Cause register is set to 1.
When the MIPS16 instruction is enabled, the EPC register contains the address of the instruction that caused the
exception, and the least significant bit stores the ISA mode in which an exception occurs. However, if this
instruction is in a branch delay slot or is the instruction following the Extend instruction, the EPC register contains
the address of the preceding jump or Extend instruction, and the BD bit of the Cause register is set to 1.
(c) Servicing
The kernel uses the failed virtual address or virtual page number to identify the corresponding access control bits.
The page identified may or may not permit write accesses; if writes are not permitted, a write protection violation
occurs.
If write accesses are permitted, the page frame is marked dirty (/writable) by the kernel in its own data structures.
The TLBP instruction places the index of the TLB entry that must be altered into the Index register. The word data
containing the physical page frame and access control bits (with the D bit set to 1) is loaded to the EntryLo register,
and the contents of the EntryHi and EntryLo registers are written into the TLB.