參數(shù)資料
型號: ST7FLIT19B
廠商: 意法半導體
英文描述: 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述: 8位微控制器單電壓閃存存儲器,數(shù)據(jù)EEPROM,模數(shù)轉換器,5計時器和SPI(內(nèi)部鋼筋,鎖相環(huán),藝發(fā)局,人事,電感,國際檢察官聯(lián)合會的SPI的8位微控制器)
文件頁數(shù): 90/155頁
文件大?。?/td> 2968K
代理商: ST7FLIT19B
ST7LITE1xB
90/155
1
SERIAL PERIPHERAL INTERFACE
(Cont’d)
11.4.6 Low Power Modes
11.4.6.1 Using the SPI to wake up the device
from Halt mode
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring
the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
state immediately.
Caution:
The SPI can wake up the device from
HALT mode only if the Slave Select signal (exter-
nal SS pin or the SSI bit in the SPICSR register) is
low when the device enters HALT mode. So, if
Slave selection is configured as external (see
Sec-
tion 11.4.3.2
), make sure the master drives a low
level on the SS pin when the slave enters HALT
mode.
11.4.7 Interrupts
Note
: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Mode
Description
WAIT
No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
HALT
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
SPI End of
Transfer Event
Master Mode
Fault Event
Overrun Error
SPIF
SPIE
Yes
Yes
MODF
No
OVR
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