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| 型號(hào)： | ST7FLIT19B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU) |
| 中文描述： | 8位微控制器單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，5計(jì)時(shí)器和SPI（內(nèi)部鋼筋，鎖相環(huán)，藝發(fā)局，人事，電感，國(guó)際檢察官聯(lián)合會(huì)的SPI的8位微控制器） |
| 文件頁(yè)數(shù)： | 30/155頁(yè) |
| 文件大?。?/td> | 2968K |
| 代理商： | ST7FLIT19B |
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ST7LITE1xB
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7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Note:
A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to
section 12.2.1 on page 105
for further de-
tails.
7.6.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the V
DD
supply voltage is
below a V
IT-(LVD)
reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The V
IT-(LVD)
reference value for a voltage drop is
lower than the V
IT+(LVD)
reference value for power-
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
V
DD
is below:
– V
IT+(LVD)
when V
DD
is rising
– V
IT-(LVD)
when V
DD
is falling
The LVD function is illustrated in
Figure 18
.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum V
DD
value (guaranteed for
the oscillator frequency) is above V
IT-(LVD)
, the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes
:
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be se-
lected by option byte.
Use of LVD with capacitive power supply: with this
type of power supply, if power cuts occur in the ap-
plication, it is recommended to pull V
DD
down to
0V to ensure optimum restart conditions. Refer to
circuit example in
Figure 106 on page 133
and
note 4.
It is recommended to make sure that the V
DD
sup-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Figure 18. Low Voltage Detector vs Reset
V
DD
V
IT+
(LVD)
V
IT-
(LVD)
RESET
V
hys
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| ST7FLIT19BF0B6 | 功能描述:8位微控制器 -MCU ST7LITE1xB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLIT19BF0BX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI |
| ST7FLIT19BF0M3 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLIT19BF0M6 | 功能描述:8位微控制器 -MCU ST7LITE1xB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLIT19BF0MX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI |
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