參數(shù)資料
型號(hào): ST7FLIT19B
廠商: 意法半導(dǎo)體
英文描述: 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述: 8位微控制器單電壓閃存存儲(chǔ)器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,5計(jì)時(shí)器和SPI(內(nèi)部鋼筋,鎖相環(huán),藝發(fā)局,人事,電感,國際檢察官聯(lián)合會(huì)的SPI的8位微控制器)
文件頁數(shù): 105/155頁
文件大?。?/td> 2968K
代理商: ST7FLIT19B
ST7LITE1xB
105/155
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92
Replace an instruction using direct, di-
rect bit or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
PIY 91
Replace an instruction using X indirect
indexed addressing mode by a Y one.
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
Note:
A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
Load and Transfer
Stack operation
Increment/Decrement
Compare and Tests
Logical operations
Bit Operation
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
Unconditional Jump or Call
Conditional Branch
Interruption management
Condition Code Flag modification
LD
PUSH
INC
CP
AND
BSET
BTJT
ADC
SLL
JRA
JRxx
TRAP
SIM
CLR
POP
DEC
TNZ
OR
BRES
BTJF
ADD
SRL
JRT
RSP
BCP
XOR
CPL
NEG
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
NOP
RET
WFI
RIM
HALT
SCF
IRET
RCF
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